SUZAKU-V FPGA specifications and development environment

FPGA Specifications

The following are SUZAKU-V's FPGA specifications. Hardware specifications can be found here.
Model SZ410-U00 SZ310-U00
FPGA Device Xilinx Virtex-4 FX XC2VP4-FG256 Xilinx Virtex-II Pro XC2VP4-FG256
CPU Core PowerPC 405 (32bit RISC core)
CPU Clock 350MHz 270MHz
Crystal Oscillator 100MHz 3.6864MHz (frequency multiplied by FPGA's internal DCM)
Serial Port FPGA internal 1ch (OPB UART Lite)
Timer PowerPC internal timer
Configuration SPI Flash TE7720 (Tokyo Electron Device)

Default Core Details
Core Version Base Address
ppc405 2.00.c
plb_sdram_emc_arb 1.00.a
plb_emc 2.00a C_MEM0_BASEADDR 0xF0E0_0000
C_MEM1_BASEADDR 0xF000_0000
plb_sdram v1.00e C_BASEADDR 0x0000_0000
proc_sys_reset 1.00.a
plb_v34 1.01.a
opb_v20 1.10.a
plb2opb_bridge 1.00.b C_BASEADDR 0xFFFFC000
plb_bram_if_cntlr 1.00.b C_BASEADDR 0xFFFFC000
bram_block 1.00.a
opb_uartlite 1.00.b C_BASEADDR 0xF0FF2000
opb_intc 1.00.c C_BASEADDR 0xF0FF3000
opb_gpio 1.00.a C_BASEADDR 0xF0FFA000
external_int 1.00.a
    * Produced with ISE7.1i, SZ310-U00

Default Resource Status
Resource Used Available Utilization
Number of BUFGMUXs 3 16 18%
Number of DCMs 2 4 50%
Number of External IOBs 69 140 49%
Number of LOCed IOBs 69 69 100%
Number of JTAGPPCs 1 1 100%
Number of PPC405s 1 1 100%
Number of RAMB16s 8 28 28%
Number of SLICEs 1897 3008 63%
    * Produced with ISE7.1i, SZ310-U00

FPGA Development Environment

FPGA development requires the following software and hardware.
  • A computer capable of running ISE and EDK (Windows XP/2000, Solaris or Linux)
  • Xilinx Logic Design Tool ISE 6.2i or above
  • Xilinx Embedded Development Kit EDK 6.2i or above
  • JTAG Cable: Xilinx Parallel Cable 4 or compatible
  • FPGA Programming Software (LBPLAYER2 included)
  • HDL simulator (ModelSim, Active-HDL etc)