The PowerPC 405 D5 is a implementation of the PowerPC 405 as a hard processor core in the Virtex-II Pro FPGA series.
Architecture
The PowerPC 405 is a RISC microprocessor family which have compatibility with the PowerPC architecture instruction set. The PowerPC 405 D5 implementation has the following features:
- 400MHz clock
- 5 stage instruction pipeline
- Harvard architecture
- 32x32 bit general-purpose registers
- MMU
- 16 KB 2-way set-associative instruction and data cache
- JTAG
Used by...
- SUZAKU-V (Virtex II Pro)
Related Links
- IBM - Power Architecture
- IBM - PowerPC 405 Embedded Cores
- IBM - Power.org
- Xilinx - PowerPC 405 Processor (D5)
- Xilinx - PowerPC Processor Reference Guide
- Xilinx - PowerPC 405 Processor Block Reference Guide
- Wikipedia - PowerPC