The PowerPC 405 is an embedded processor core which utilizes the PowerPC Embedded-Environment Architecture.

Architecture

The PowerPC 405 has the following characteristics:

• PowerPC user instruction set architecture
• 5 stage pipeline
• 32 x 32 bit general-purpose registers
• Hardware multiply and divide
• 16 KB two-way set-associative instruction and data cache
• MMU
• 64-entry fully-associative TLB
• Variable page sizes (1KB - 16 MB)
• IBM CoreConnect™ bus architecture support
• Debug and trace support

Related Links

• This site - PowerPC 405 Processor D5 (Virtex-II Pro implementation)
• IBM - Power Architecture
• IBM - PowerPC 405 Embedded Cores
• IBM - Power.org
• Wikipedia - PowerPC